IT Minister commissions ‘India Validation Centre’ to build resiliency in chip making


Bengaluru, Mar 9 (IANS): Union IT and Telecom Minister Ashwini Vaishnaw on Saturday commissioned the India Validation Centre (IVC) at semiconductor company Applied Materials India here, which will enable early pilots, talent and capability development for the upcoming India Collaborative Engineering Centre.

The centre will add new capabilities to enable end-to-end design, characterisation and qualification of semiconductor equipment.

US-based Applied Materials also demonstrated the capability to process 300 mm wafers at IVC, a first for the private industry in the country.

“Under the leadership of Prime Minister Narendra Modi, India’s semiconductor ecosystem has achieved significant growth over the past few years,” the minister said.

“The India Validation Centre is a testament to the dedication and effectiveness of our approach to build India’s resiliency in chip manufacturing, and Applied Materials has been a trusted partner in enabling the Indian semiconductor dream,” he added.

Following PM Modi’s meeting with Gary E. Dickerson, President and CEO of Applied Materials, during his visit to the US last year, the company announced plans to build a collaborative engineering centre in Bengaluru with an investment of $400 million spanning over four years.

According to Ashwini Vaishnaw, this centre “will further help develop manufacturing capabilities in the sector and exemplify the trust that global companies have placed in India".

Prabu Raja, President of the Semiconductor Products Group at Applied Materials, said, “We will continue to develop our capabilities in India to support our customers and work with supply chain partners to strengthen the local ecosystem and help India’s semiconductor industry succeed.”

Applied Materials, the leader in materials engineering solutions, used to produce virtually every new chip and advanced display in the world.

 

  

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Title: IT Minister commissions ‘India Validation Centre’ to build resiliency in chip making



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